Logic-synthesis tools take the tedium out of logic design. (includes a related article on how to...

Logic-synthesis tools allow time for the creative aspects of application-specific integrated circuit (ASIC) design by automating tedious tasks. They also ensure error-free realization and help shorten design cycles. Expectation should be realistic, logic synthesis is most effective when the user becomes proficient with the tool. Design description will affect the tool's efficiency. Synthesis tools work best on smaller partitions. Reduced area implies reduced gate count; a reduced source of delay. Back-annotated netlists will perform differently. Random-logic netlists can reduce traceability