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Brion, TOOL Corp. Unveil Integrated IC Design Environment.

TOOL's Layout Visualization Platform, LAVIS, Combined with Brion's Computational Lithography System, Tachyon, Addresses All Stages in Design for Manufacturing Flow

SANTA CLARA, Calif. -- TOOL Corp. and U.S.-based Brion Technologies Inc. today announced

the successful development of an integrated IC design environment that incorporates both TOOL's versatile layout visualization platform, LAVIS, and Brion's highly accurate and ultra-fast OPC and RET/OPC verification system, Tachyon.

This integrated environment is an essential tool for semiconductor fabs, photomask shops and fabless IC design houses that pursue design for manufacturing (DFM) solutions now and in the future. TOOL and Brion have combined LAVIS' large-volume data handling and high-speed data display capabilities, which can utilize all the data formats used throughout the chip design processes, with Tachyon, a manufacturing-proven computational lithography platform that is able to execute high-speed, full chip simulation and inspection with high precision.

This integrated environment can first display chip design data with LAVIS, conduct lithography simulation of designated areas of that design within Tachyon, and then display the results again with LAVIS. Because design data and simulation parameters are seamlessly and automatically communicated between LAVIS and Tachyon, the user is able to easily obtain simulation results without difficult and complex data preparation.

"TOOL and Brion's integrated design environment is most welcome," said Hiroshi Sakuma, general manager of NEC Electronics Corp.'s Technology Foundation Development Operations Unit, Design Engineering Division. "Hot spots are already becoming an issue with leading edge IC designs, and these problems will only increase with future technology nodes. The ability to perform Tachyon's high precision lithography simulation easily and repeatedly through LAVIS' design environment is critical to solving problematic hot spots."

As chip geometry continues to shrink from 65nm designs to 45nm and then 32nm, device patterns are becoming more complex because of the optical proximity correction (OPC) used to ensure that sub-wavelength features in these patterns are transferred correctly onto silicon. To achieve accurate OPC, it is critically important for high-speed, accurate simulation to verify design data and OPC data during the design process, which is provided by Brion's Tachyon.

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