New book on Chip Scale Packaging. (Up Front).

In recent years, front-end semiconductor manufacturing has driven down the cost and size of wafer fabrication at a more rapid pace than back-end die packaging operations. As such, we have arrived at a juncture where packaging the silicon adds a disproportionate share of size and cost to the final product....

The first annual International Wafer-Level Packaging Congress (IWLPC) to explore semiconductor packaging and test technologies, with special emphasis on three-dimensional (3-D) stacked packaging, will be presented in San Jose, CA, on Oct. 10-12. The congress and exhibition are sponsored jointly by the Surface Mount Technology Association (SMTA, Minneapolis, MN, www.smta.org) ......

The past few decades have seen several basic shifts in electronic packaging that have impacted the whole industry. The introduction of surface-mount technology (SMT) and ball grid array (BGA) packages were important steps for high-throughput assembly of a wide variety of IC types, while at the same time allowing reduction ......

Future looks bright for BGAs, CSPs and wafer-level packages. With slower growth projected for 2001, compared to the rapid growth in the electronics industry last year, companies are concerned that shipments of emerging packages might not meet expectations. Yet, while the rate adoption of some emerging packages might slow slightly, ......

The merger of Electronic Packaging & Production (EP&P) into Semiconductor International creates exciting opportunities for expanded coverage of back-end semiconductor technologies in the business press. Innovation is becoming a hallmark of the back-end technologies as they seek to emulate front-end automation, find common technical ground and generate larger proportions of ......

There is no doubt that 3D chip scale packaging technology will play an increasingly vital role in meeting performance and size requirements for future generations of mobile electronics, according to a new report by market research firm VDC. While ball grid array and chip scale package options have decreased package ......

There is no doubt that 3D chip scale packaging technology will play an increasingly vital role in meeting performance and size requirements for future generations of mobile electronics, according to a new report by market research firm VDC. While ball grid array and chip scale package options have decreased package ......