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Rethink fault models for submicron-IC test.(Technical)

By Garcia, Rudy
Publication: Test & Measurement World
Date: Monday, October 1 2001

The design and test community must examine stuck-at, stuck-open, transition, path-delay, and [I.sub.DDQ] fault models to cut test escapes.

The electronics industry is in the midst of a transformation that is drastically changing product design and manufacture. Deep submicron process technology puts more gates on a chip, and the gate-count escalation enables the industry to make major strides toward producing smaller and faster computing, communications, and entertainment products.

The increasing design complexity and reduced error margins in semiconductor m

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