Joe Sawicki, Vice President, Mentor Graphics

Joe Sawicki is vice president and general manager of the design-to-silicon division of Mentor Graphics (Wilsonville, Ore.). As such, he is responsible for the Calibre design-to-silicon platform, including physical verification, parasitic extraction, resolution enhancement, mask data preparation (MDP)

and design for manufacturability (DFM) products. After eight years as an IC designer, Sawicki joined Mentor Graphics, where for 13 years he has held positions in applications engineering, sales, marketing and management. Sawicki holds a BSEE from the University of Rochester and an MBA from Northeastern University's High Technology Program. Mentor Graphics is a leader in electronic design automation (EDA).

SI: How does the role of the CTO of an EDA company differ from that of a device manufacturer?

Sawicki: Something that's different here is that we don't have a corporate-wide CTO. Inside the division, we have a number of people working officially or unofficially in chief scientist positions. In many ways, my role is more about translating longer-term trends and getting them to work on things that yield in the medium term.

SI: So you act as a compass?

Sawicki: (Smiling) Sort of, only someone else provides the magnetic field. You just try to pick up the strongest signal and ensure it's properly aligned. For instance, from a technology perspective, RET probably is the most significant thing in years that we've done here. At 180 nm, you could smell it coming, but the fundamental reason we were successful is that we bought a company that had strong technologists who were a few years ahead of the software curve. This is interesting to me, because EDA almost always is said to be a step or two behind the technology curve; yet, there would be no technology node at 130, 90 and 65 nm were it not for the EDA tools doing the OPC right now.

SI: As a planner for an EDA company, do you find the ITRS useful?

Sawicki: The roadmap has always been useful to arrive at an understanding about where technologies must progress. Particularly the last one, where it stopped focusing on a node and recognized that there will be different nodes for different platforms. From a conceptual perspective, that's something very useful to look at. Certainly, when you consider enabling a memory design vs. a logic design, the impetus it gives the software is different — two dissimilar worlds on how we do that type of processing.

SI: What parts of the roadmap are most interesting to you?

Sawicki: As we look at the red bricks, we try to figure out where there are known avenues to solutions, since these are opportunities. I look at things like the specs for cross-field linewidth variation, which are delusional and have been for years, but which can be used as indicators about what one needs to do to manage error sources in the flow.

SI: What does your technology roadmap look like for the next five years?

Sawicki: Our focus has begun to switch. Most of our advanced R&D is currently looking at 45 nm development, with 32 as a logical extension. We're making some assumptions — one is that we're going to get wet litho to work. Without it, everything gets very foggy. We're also counting on getting some big glass with high NA going into the wet system. Those two pretty well map out what's needed in terms of our software development efforts, at least for the next four years. It's mostly to do with dealing with aberration issues in the lenses, water polarization effects, and we're also going to have to look at the mask's topology and how its non-planarity will affect the overall image making. All of these will drive pretty heavily through 32 nm, and then after that, all bets are off.

SI: And when your users get the 45 nm software, they'll try to use it for 32 and beyond.

Sawicki: Of course! I feel comfortable that you'll be looking at some sort of 32 nm with 193. Beyond that, the crystal ball gets cloudy.

SI: As shrinks continue — particularly since no EDA company produces its own models, which originate from academia and other sources — how do you cope with things like transistor parameters shifting as a function of time, where you must provide performance at the transistor level and at the interconnect level, as well as deal with power dissipation, speed performance and the other various trade-offs?

Sawicki: We began seeing this gaining in importance some two years ago, as we considered post-layout validation; thus, we became heavily involved with the Compact Modeling Association. Currently, we're one of the chairs of a subgroup considering how to do physical parameter extraction and map it into whatever the replacement for BSIM4 will be. We're becoming more involved not in writing models, but in driving what the parameter space is going to be for those models. Another interest area is that for years we've been doing an increasingly complex extraction based upon drawn layout, and then fed them into simulation and assumed drawn dimensions would match to the silicon. This was a rational assumption in the past. This is no longer the case.

SI: Why?

Sawicki: The lower you get in k1 , the more difficult it is to produce rectilinear transistors. We statistically average those changes over a chip and assume that this will be close enough. I don't think this can continue, which is why a considerable portion of our development effort is aimed at moving the litho side into the design side. That way, rather than trying to get a statistical approximation of what these transistor profiles will be, we can deterministically map them to understand how the distortions affect local performance. In both cases, we're getting more involved in how you do and use transistor modeling.

SI: Not a simple matter.

Sawicki: Indeed. You can make simple approximations when you begin things. One of the first things we're looking at, just to show prototype behavior, is taking the device's real profile, make a rectilinear approximation of the number of transistors (some in parallel) and determining what this tells you about what these effects should be. That gets you to understand that there is something going on, but it does not provide the final answer, which is extremely complex.

SI: What is the status of models and modeling today?

Sawicki: What's out there now isn't going to move forward. If you look at the Band-Aids we're trying to use to get stress-effect models and the like, this isn't going to track. This is why we're more involved in attempting to define what the models will need to be, and judging which models will be accepted. The biggest issue still open is whether to continue to do assumptions about the device profile, or somehow push it in from a deterministic litho perspective. The EDA industry can no longer take a passive approach toward modeling. Now, if we don't get what we need, it's as much our fault as that of the model provider.

SI: You indicated you're already working with 90 nm. Looking at 65 nm, how do you support the signal integrity concerns at those geometries?

Sawicki: There are two levels of signal integrity. One is where you must do very quick rule-driven, full-chip work for the digital domain. We don't do those tools. The other aspect of signal integrity is looking at it from a deterministic small-scale perspective, when you are looking at analog blocks, analog digital interfaces. What we see as interesting and where we do have an impact is in managing and simulating the analog/digital interface. As you get increasingly more designs that are dependent upon the interface between analog and digital, a simple spec no longer is sufficient. Our effort here has been toward doing signal integrity, doing simulation on analog and digital mixed-signal environments.

SI: What are you doing in the areas of DFT and BIST?

Sawicki: We've been part of these two sides of test for several years, and have a significant presence in both. Our test solutions include not only scan-based design, but also BIST for logic and memory. As of a couple years ago, it became clear that as fault models become more subtle, the amount of vector coverage needed to hit those — whether they are at speed faults, via voiding, etc. — increases exponentially. Many more vectors will be needed to cover the same percentage of failure rate. We have a tool that blends some of the best worlds of BIST and scan, and it is embedded deterministic test. This gives 100× compression at times, from the amount of vectors that are needed in the machine vs. the coverage available internally. Defects are becoming more difficult to detect, and one also needs to look at them as a way of learning about yield. We're working to tie the physical with the test tools to do more yield analysis. We can track failure logs, deterministically find out where the faults were, and use the physical information to pinpoint those to particular regions or effects on the chip. Thus, test no longer is just a way to screen parts, but also a key component of the fab's yield managing system.

SI: More vectors mean more complicated algorithms, requiring more computing power. Are you comfortable with the computing resources?

Sawicki: In 2000, we released the first multiprocessing version of one of our tools. It was a threaded version that ran on SMP machines. We got good scalability; however, when looking at the roadmap and seeing that k1 is going from ~0.35 to ~0.25, which means that the OPC complexity increases by about a factor of 10, the number of shapes by a factor of 16, the math requires an SMP box with 128 processes — can you afford it? So we started on a distributed version of our technology some three years ago. Software is more flexible and robust than hardware in tackling challenges, since by definition, hardware is frozen. So I'm comfortable with the compute platforms.

SI: How do you see the fact that packaging is becoming a part of the circuit?

Sawicki: We must start looking at bridging the two worlds of PCB and IC design, and determine how to manage signal integrity, not just on chip, but as it goes out through leads onto the board. I'm unsure how that ends out playing out in terms of the exact technology offerings and what they look like. I do know that it'll be difficult to manage this without experience in both domains. We're not talking red bricks here, just yellow bricks.

SI: If you had unlimited resources to devote to a single problem, which would you choose?

Sawicki: I am fascinated by how variability, especially in the litho space, affects design. It's difficult to imagine a world where we can get away, at 32 nm, with simple digital models that tell me how much capacitance I'm driving and I'll tell you how much performance I am going to get. This problem is going to become pervasive, affecting our entire design chain. What makes this particularly exciting is that you can't just do R&D back in your software development lab. Figuring out how variability is going to hit and move from the processing space into design is something you must do with customers working on real fab processes.