LogicVision First to Enable Structural Test Signoff in VHDL With Model Technology's HDL...

Business Editors/Technology Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 28, 2001

LogicVision, Inc., a leading provider in embedded test for integrated circuits and systems, today announced an interface that enables test verification signoff for both Verilog and VHDL designs using

Model Technology's ModelSim(R) simulator and LogicVision's embedded test solution. The interface includes the industry's first parallel load simulation capability for VHDL scan-based designs, substantially accelerating test verification by as much as 1000x depending on the length of the scan chains.

"Structural test is the only cost-effective way to test multimillion-gate designs," said Jeff Vanderlip, director of ASIC Marketing at LSI Logic Corporation. "LogicVision's embedded test solution is the first to enable structural test signoff in VHDL."

Today, most ASIC designs must signoff with a Verilog netlist due to the lack of VHDL support from test and layout tools. ASIC designers who verify their RTL design in VHDL must translate their design to a Verilog format for their gate-level signoff verification. Using special function calls provided in ModelSim, LogicVision has developed a VHDL simulation interface that loads scan data directly into all the scan flops in a design in parallel. The parallel load capability eliminates the long process of simulation cycles used for shifting data through scan chains and expedite simulation of ATPG and BIST vectors by orders of magnitude.

"The functions provided in ModelSim enable VHDL simulation to have the same access to internal nodes available for Verilog simulation through the Verilog Programming Language Interface," said Dennis Brophy, director of strategic business development at Model Technology "Together with the 2-4X performance increase available in ModelSim 5.5, designers can now signoff in the language of their choice."

Rodger Sykes, vice president of marketing and business development at LogicVision said "LogicVision's ModelSim interface is now available in our latest Embedded Test product," he adds "We are pleased to have Model Technology's cooperation and support of our development effort. ModelSim is clearly the preferred simulator for our VHDL customers."

About LogicVision

LogicVision provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com.

    Acronyms and definitions:

ATE: Automatic Test Equipment
ATPG: Automatic Test Pattern Generation
BIST: Built-in-Self-Test
DFT: Design-for-Test
EDA: Electronic Design Automation
HDL: Hardware Description Language
IC: Integrated Circuit
RTL: Register Transfer-Level
VHDL: VHSIC (Very High-Speed Integrated Circuit) HDL
IP: Intellectual Property
SOC: System-on-chip