Avery Design Systems Accelerates ATPG/BIST Pattern Validation.

ANDOVER, Mass. -- Avery Design Systems Inc., an innovator in functional verification, today announced improved support for simulation acceleration of ATPG/BIST pattern validation using its SimCluster parallel simulation solution with the release of automatic scan path partitioning and support for

"While functional gate-level simulation has been deemphasized in today's verification methodologies, ATPG/BIST validation is still essential but made overly difficult for today's multi-million gate designs due to the poor simulator performance and excessive process memory size requirements," said Chilai Huang, president of Avery Design. "SimCluster eliminates these bottlenecks by generating a multi-process, parallel ATPG/BIST simulation that runs in 1/10 the time and better exploits 32- and 64-bit compute platform resources."

The auto-partitioner tool reads a flattened or hierarchical design netlist and ATPG/BIST testbench and partitions the database into multiple simulation targets. Scan-path partitioning enables the user to allocate one or more scan chains to different simulation partitions including the behavioral scan controller generated by the ATPG tool when writing out the patterns. This approach yields optimal performance by minimizing the communications overhead of parallel scan load, unload, and compare steps.

SimCluster 3.0 also adds support for 64-bit Linux and Solaris operating systems which can be used in conjunction with simulators running in 64-bit mode. However the auto-partitioner may also be directed to target partitions that fit within 2-4 GB process size thus enabling the simulation to run on 32-bit platforms.

About SimCluster

SimCluster unleashes the power of distributed computing for RTL and gate-level simulation and delivers scalable simulation performance of 5-15 X speedup or more. SimCluster simulates full-chip SOCs by allocating its subsystems to multiple tightly synchronized simulators running in parallel on 2 or more interconnected computers. SimCluster results are fully deterministic and can be tuned for optimal performance.

About Avery Design Systems

Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com.