Copper Stud Bumping for Flip-Chip Applications

Approaching 10% of the entire interconnection market, flip-chip devices are one of the highest growth segments of semiconductor assembly. However, higher assembly cost has hampered flip-chip growth in consumer electronics, limiting its adoption to applications with requirements for a smaller footprint

Copper stud bumping, which uses a high-speed automatic wire bonder with the addition of a kit to enable copper ball formation in a protective atmosphere, has the potential to significantly lower the cost of ownership for the flip-chip process. For low- to medium-I/O devices such as DDR3 DRAM, automotive applications, and sensors, copper stud bumping is significantly less expensive than conventional sputter/print solder paste or electroless plating methods. Incorporating wire bond technology as a part of the flip-chip bumping process is attractive because existing facilities and infrastructures can be used without the high capital costs required by more expensive sputter/plating facilities.

A joint project between Delphi Electronics & Safety and Kulicke & Soffa has produced and tested prototype parts using low-cost copper stud bumping combined with stencil-printed solder paste. Figure 1 illustrates a typical cross-section through a flip-chip assembly employing copper studs. Initial results were very promising, meeting all mechanical requirements. Although long-term reliability testing (thermal cycling) did not meet the most severe requirements for automotive underhood applications, they exceeded lower requirements for computers, cell phones and office products.1 Additional experimentation and optimization will be required to pass the stringent automotive requirements. Low-cost flip-chip assembly using copper stud bumps will provide an easier implementation path for companies unable to justify the significantly higher capital equipment costs of conventional sputter stencil or electroless nickel/gold processes.

Technology overview

The growth of flip-chip from a niche portion of the interconnection market requires the development of lower-cost processes and materials. Generally, flip-chip interconnects are solder — either SnPb or lead-free — which is deposited at the wafer level (i.e., wafer bumping). Solder application can take many forms, including electroplating, evaporation and printing solder paste. Although each method is employed in volume manufacturing, their merits are actively debated. Often overlooked, the underbump metallization (UBM) plays a critical role in joint integrity as an intermediate layer providing a solderable surface while preventing interdiffusion to the IC. In particular, UBM must exhibit low stress, excellent adhesion, corrosion resistance and solder wettability over the expected product life. In accelerated tests, flip-chip joints constructed with a properly designed UBM are limited by solder fatigue. Only vacuum deposition of multiple metal layers (i.e., a sputtered trilayer of Al/Ni/Cu) has proven capable of maintaining these joint reliability requirements. Vacuum deposition is expensive and requires highly skilled operators to run and maintain equipment. These costs do not increase linearly with wafer size, pricing out all but the largest manufacturers, who, in turn, increase throughput by eliminating any flexibility to process different wafer sizes.

Figure 2 illustrates a conventional flip-chip process. UBM layers are grown on the chip during wafer fabrication using photolithographic processes, which require additional mask development. UBM not only provides an adhesive layer for the solder, but also acts as a solder stop. The solder does not adhere to the chip passivation layer, so bridges between adjacent solder balls are avoided. After the solder is applied, it is reflowed (melted) to form spheres (balls). Lower-cost flip-chip processes may use electroless nickel instead of a sputtered UBM. Figure 3 illustrates the electroless nickel flip-chip process. Electroless nickel requires a wet chemical process. The aluminum bond pads are first double-zincated. A thin zinc seed layer is formed on the aluminum to provide a sacrificial layer for nickel adhesion. The zincate process is often performed twice to increase uniformity of the seed layer. After the zinc layer is formed, electroless nickel reacts with the zinc in a substitution reaction. Zinc atoms coating the aluminum surface are exchanged with nickel atoms to form a thin coating that continues to grow until thickness reaches 5 µm. The nickel pad is then plated with a thin gold cap for passivation. The nickel/gold pad provides a base for screening solder, which is subsequently reflowed to form a sphere.

Copper stud flip-chip

Copper stud bumps provide a base for solder adhesion without requiring UBM2 or electroless nickel/gold bumps, simplifying the process because they do not require additional wafer fabrication or plating operations. Copper stud bumps are formed with a modified automatic wire bonder at high speeds. Figure 4 illustrates a copper Accu-Bump, and Figure 5 illustrates the assembled structure. For devices with low to medium I/O count, such as automotive and DDR3 DRAM, they provide a low-cost-of-ownership (CoO) path to high-quality bumping, requiring less capital costs and process steps than traditional UBM methods. They also have the potential of achieving a finer pitch than conventional flip-chip through the use of existing wire bonding capabilities.

The formation of stud bumps is a variation of the wire bonding process. The wire bonder forms a ball on the tip of a wire protruding from the capillary. The capillary then descends to the work surface and bonds the ball. Instead of moving on to form a wire loop, as in a typical wire bond, the capillary rises and terminates the wire above the ball before forming a new ball and repeating the process. In the case of the Accu-Bump, additional motions occur during the wire termination to produce a flat-shaped bump, preferable for flip-chip. Stud bumping is significantly faster than wire bonding, because all of the looping motions of normal wire bonding are not needed. Standard copper bump speed is up to 32 bumps/sec. Accu-Bumps can be formed at up to 27 bumps/sec for copper.

Copper stud bumps typically have shear strength of ~110 MPa, comparable with that of the aluminum bond pad. Intermetallic growth in the copper aluminum system is extremely slow, with no known intermetallic voiding mechanisms as in the gold aluminum system. Once a copper aluminum weld is formed, it appears to be stable and have good long-term reliability. As copper oxidizes, it must be cleaned prior to solder screening in order to promote good adhesion by removing stubborn oxides on its outside surface.

Once the solder is screened on the stud, the chip is placed on the pre-fluxed site on the substrate and reflowed. The capillary underfill is dispensed and cured after the cleaning of the solder residue. The stud bump can alternatively be assembled using no flow underfill (NFU). NFU enables a single reflow that simultaneously attaches the bump to the substrate and cures the underfill. Even though the copper bump is a high-strength interconnection, the solder (tensile strength, 37 MPa; creep strength, ~3 MPa) remains the weak link mechanically. Underfill bonds to both the chip and substrate, mechanically strengthening the integrity of the joint for improved fatigue strength during thermal cycling.

Redistribution layers (RDL) are often used to map devices with a peripheral wire bond layout to a larger pitch, area-array flip-chip layout for solder bumping. The cost of RDL can add significantly to a wafer's total cost. The RDL not only changes the layout from peripheral to area array, but also allows screen-printing of larger solder bumps. The RDL process is not required for stud bumping.

An initial collaboration between Delphi and K&S has demonstrated the low-cost feasibility of this technology. Delphi (open source, commercially available) wafers and substrates were used for a performance evaluation. The test die and substrates included a matched die and substrate, designed for testing using a daisy-chained peripheral bond pad layout. Each die had 48 I/Os. Chips with higher distance from the neutral point (DNP, distance from the center to the furthest bump) have more difficulty with fatigue (thermal cycling) because they have the largest differential displacement between the chip and substrate (strain). These devices had a DNP of 2.8 mm. Die were bumped at K&S on the AT Premier bonder and shipped to Delphi, where they were assembled using the traditional capillary flow underfill process. Assembled die and substrates were thermal-cycled to failure (-50 to 150°C), with resistance change monitored through the daisy chain. The criteria for failure was a 10% increase in electrical resistance. Resistance of the (48 I/O) daisy chain was ~1 Ω. Figure 6 provides the thermal-cycle failure data, and Figure 7 shows a cross-section through the high-resistance bumps. Failures were attributed to the copper bump/aluminum bond pad interface. Although these results did not meet stringent automotive underhood criteria, they were sufficient to meet most cell phone/computer/office product criteria (-40 to 125°C, 300-800 cycles). Additional experimentation is expected to provide the needed reliability for automotive specifications.

Bumping CoO model

CoO modeling is a method for analyzing competing processes and determining a fully loaded cost comparison. Where individual operations may have different costs, an analysis of all the cost and manufacturing parameter differences is necessary to arrive at the total cost of product manufacturing. In the case of flip-chip bumping, this comparison shows that, when the number of bumps/wafer is in the low to medium range, copper stud bumps are less expensive than bumping with either electroless nickel bumps or conventional sputter/stencil solder bumps. The transition is not only dependent on the number of bumps required per wafer, but also on the cost and speed of the equipment. High-speed bonders provide the additional production capability required. For conventional sputter/stencil or electroless nickel bumps, the cost of bumping is fixed by wafer size and is independent of bump quantity. Figure 8 shows the relationship. As bump density/wafer increases, costs increase and conventional flip-chip processes are less expensive. But for low- to medium-I/O devices that do not require high bump density, such as DDR3 DRAM, automotive controls, etc., the stud bumping process is less costly. For 200 mm wafers with <400,000 bumps, copper stud bumping has a cost advantage. Additionally, this analysis does not include intangibles. Many assemblers have a large base of installed wire bonders with trained operators. Adding wafer bumping does not require significant factory changes. Conventional flip-chip bumping is a significant change requiring expensive capital equipment and facilities. Figure 9 is a breakdown of stud bumping costs by operations. Administrative costs include all of the labor; capital includes the costs of equipment; and variable costs include all materials and consumables.

Conclusions

The copper stud flip-chip process has demonstrated feasibility as a low-cost alternative to sputter/stencil or electroless nickel/gold processes. Although it did not initially meet the most stringent reliability criteria, further work is expected to achieve even these high standards. Copper stud bumping can, potentially, provide the lowest-cost flip-chip process for devices with low to medium I/O density, such as DRAM and automotive applications.

Lee Levine is a senior member of the technical staff for Kulicke & Soffa's advanced packaging ball bonder division. In 1997, he received the John A. Wagnon Technical Achievement Award from the International Microelectronics and Packaging Society (IMAPS). He has been granted four patents and has numerous published works. Prior to joining K&S, he was senior development engineer at AMP Inc. and chief metallurgist at Hydrostatics Inc. Levine received a bachelor's degree in metallurgy and materials science engineering from Lehigh University (Bethlehem, Pa.).

Arun Chaudhuri has been a staff engineer with Delphi Corp. since 1991. Prior to Delphi, he worked for GTE and Air Products & Chemicals. He has published more than 12 technical papers and has been granted several patents. Chaudhuri was recently inducted into the Hall of Fame at Delphi. He has a Ph.D. in chemical engineering from the Indian Institute of Technology, Kharagpur, India.

Frank Stepniak recently joined the technical staff at Texas Instruments (Dallas), supporting the packaging organization of high-performance analog. He spent the previous 10 years at Delphi. He has been granted 10 patents and has over 20 published works focusing on enhanced reliability of flip-chip packaging in harsh environments. Stepniak received a B.S. in chemical engineering from Penn State and a Ph.D. in materials science from the University of Minnesota.

References

1. L. Levine, "Look for Wafer-Level Packaging to Rule as the Natural Choice for Opto Packages," Chip Scale Review , July 2002.

2. D.F. Baldwin, "Flip Chip Interconnection Using Copper Wire Bumps," Advanced Packaging , March 2006, p. 44.

Acknowledgements

Thanks to Cuong Huynh and Deepthi Kurra of K&S for their bonding support and to the staff of K&S Bonding Wire for metallographic support.