Drawing on the lessons of using error correction to allow for the turning down of power to transmitters in radios, ARM is collaborating with researchers at the University of Michigan to apply the same concepts to silicon to gain power savings in processors.

ARM VP John Cornish, who works in the processors division of the IP (intellectual property) processor giant, offered details of the research project during his keynote address at the Fall Microprocessor Forum this week.

Cornish announced the research during a keynote that provided look at current approaches to achieve processor power reduction, such as power gating, coarse grain power switches, state retention and dynamic voltage and frequency scaling. These efforts come in an age where energy efficiency has become the limiting factor for many systems, he said.

“We’ve got a challenge as an industry to maximize the performance from a constrained energy envelope,” he said.

“People to continue to upgrade their phones, set top boxes, and MP3 players,” he said. “That means more processor performance, but that has to be accomplished within fixed or shrinking energy envelope.”

ARM’s research project with the University of Michigan looks to use error correction to change the approach designers can take.

“We design for worst case scenarios,” Cornish said. So designers look at variance, process distribution, potential inaccuracy of models and environment and build devices that will work under the worst conditions for each of these factors. But that makes for inefficient design because the highest probability is for the center of the scenario. “The worst case is improbable and it’s especially improbable for all the worst cases to happen at the same time.

“We think there are significant gains to be made by building in error correction capability rather than building for worst case scenarios,” he said. “We are familiar with this in communications space. All of radio uses error correction within its protocols to let us use lower power transmitters and save power and cost.

“The Razor approach uses similar methods,” said Cornish, “but on silicon, to enable us to get away from designing for worst case scenario.”

For example, such an approach can enable designers to allow for mistimed events. If the design can also detect and correct such an error operations can continue as normal, according to Cornish.

By using such an approach under typical case conditions for all chips, designers can gain 39 percent more energy efficiency.

“Typical case operation requires an understanding of when and how systems break,” Cornish said. “Razor specifies the microarchitectural requirements.”

But the approach requires some finesse to implement.

“There is a cost to doing error correction, too,” Cornish said. “The trick is to find the optimum point to where we are doing just enough error correction to move us away from worst case, but not consuming excessive silicon area or energy to do that error correction.”

While the approach still faces challenges, such as variations across silicon on the wafer, “this does hold out the prospect for increased energy efficiency in the future,” Cornish said.

ARM recently unveiled http://www.edn.com/article/CA6334630.html a Cortex R4 configured for 3G mobile phones.