When Austin-based Silicon Laboratories Inc. was ready to put its first chips on the market in 1997, the fabless company decided to work with a pure-play foundry that would help it manage the rising costs for photomasks. A mask set, required to transfer chip designs onto silicon, cost about $30,000, which was a relatively steep entry price for the year-old startup.

Today, that seems like a bargain price. Mask costs have spiraled into six figures for the latest generation of technology. The price for a set of masks needed to produce leading-edge chips has soared 2,300% in the past decade, starting at around $25,000 for 0.50-micron devices and jumping up to $600,000 for 0.13-micron devices, which are ramping up now. Moreover, the industry has been warned to expect to pay up to $1.5 million for the next generation (see chart, page 53). Taking chip designs to masks is Silicon Labs' second-biggest expense, after personnel, says Daniel Artusi, president and chief operating officer. "That's pretty shocking," Artusi says.

The skyrocketing costs, especially during the worst downturn in the chip industry's history, have slowed IC-design innovation, put unprecedented pressure on photomask suppliers to help their customers and spurred diverse efforts by software companies and others to blunt the price spikes. For example, leading foundries put multiple customers' designs on a single mask, so they can share costs. DuPont Photomasks Inc. , a global supplier of masks in Round Rock, TX, recently began selling software to correct design errors before the designs are sent to the mask fab.

Still, these are incremental steps and stopgap measures, says Kurt Kimmel, mask program strategy manager for the semiconductor consortium International Sematech in Austin. The hard truth is that absent technological breakthroughs, chip companies should not expect much relief from high mask costs as long as Moore's Law holds true. That famous observation made by Gordon Moore of Intel Corp. , Santa Clara, CA, in the 1960s holds that memory chip performance doubles every 18 to 24 months, or from one design node to the next. It means, for example, that reducing line and transistor widths from 0.25 microns to 0.18 microns doubles the number of transistors on a chip.

"The chip maker gets a huge benefit, but the mask maker has twice as many transistors to write at a tighter spec," says G. Dan Hutcheson, chief executive officer and president of San Jose-based VLSI Research Inc. "It's definitely a huge issue, and it's not going to go away easily."

A trick of the light

Photomasks, quartz plates several inches thick and 6 inches across, transfer chip designs onto silicon wafers in a process called optical lithography. An advanced mask set can include two dozen or more plates, or reticles. Each imparts specific design elements or layers of the chip onto the silicon. In the 1990s, mask makers were able to do extraordinary things with light to etch shrinking chip designs onto wafers. Ordinary light produces wavelengths about 0.6 microns wide, or about 1/200th the width of a human hair. By the mid-1990s, when mask makers came into their own by providing a key enabling technology for the chip industry, they used ultraviolet light and then deep-ultraviolet light, which has a wavelength of 0.248 microns.

That cleared the way for chips at the 0.25-micron node. Those mask sets cost about $100,000 initially, and the price has dropped somewhat since then. On their inexorable march toward tighter design rules, leading makers of integrated circuits soon designed chips at the 0.18-micron node, or 1/500th the thickness of a human hair. ICs at the 0.13-micron node are ramping now, with the 90-nanometer node next in the coming cycle. To keep up, mask makers have figured out how to exploit predictable behavior of light.

Using techniques called phase shifting and optical-proximity correction, they have been able to etch features on the masks that are narrower than even deep-ultraviolet light waves. Analysts, chip companies and mask makers say soaring prices primarily reflect the increased complexity of replicating the incredible shrinking circuit designs on the masks. The shrinking geometries of chips are a major factor in mask costs, requiring more time and precision for pre-paring masks, which are subject to yield issues just as chips are. Leading-edge chip designs have tens of millions of gates versus, say, 200,000 just a few years ago. The subwavelength era at 0.25 microns introduced new challenges.

All this complexity adds time to mask making and more opportunities for errors. It also helps make the case for more automation in the mask plants. A survey of leading mask makers released last year by International Sematech revealed that a surprising 18 percent of yield losses resulted from human mistakes in manufacturing and data entry.

"That means you have to throw away more masks before you get a good one," notes Gary Smith, of Gartner Dataquest, San Jose. "Mask prep is especially expensive." But Smith argues that mask costs are less of a problem for the industry than the cost of designing the chips in the first place. "The real issue is that IC design is getting far more complex than it has ever been," he says. "You may see a million-dollar mask at 90 nanometers, but the design itself costs $20 million or so."

Mask fabs behind in technology

No one is accusing the photomask industry of price gouging. The two leading U.S. mask makers, Photronics Inc. , Brookfield, CT, and DuPont Photomasks, lost money last year. Indeed, revenues for the entire industry have stalled at about $2.5 billion for the past three years, despite spiraling prices for advanced mask sets.

"The cost of equipment needed to write, imprint and repair photomasks has risen somewhat sharply," says Tom Reeves, vice president of ASICs for IBM Microelectronics , Burlington, VT. In fact, the cost of building and equipping a mask fab has grown fivefold since 1990, from about $50 million to $250 million today, according to VLSI Research. That compares to about $3 billion for a chip fab, but the price tag for those plants has remained relatively constant in recent years. Ironically, despite the escalating costs for new mask-making plants, the facilities are technological laggards compared to other fabs.

"A mask fab is years behind—a decade behind—in sophistication of equipment and in automation, process controls, software analysis systems for yield management and logistical and productivity controls," says International Sematech's Kimmel. The main reason is that mask industry vendors serve a much smaller market. Given that tools used for etching IC designs on masks may cost $6 million to $12 million, the market for such tools doesn't justify the R&D investment that vendors pour into fab equipment.

"The business case is simply not there for putting the level of money that a Nikon , an ASML Holding A.V. or a Canon pours into scanners in the hopes of selling hundreds of units per year," Kimmel says. Meanwhile, mask equipment makers "will fantasize about selling 10 systems in a year," he says. Indeed, sales of mask-making equipment slipped 31 percent last year, to $46.7 million, from $68 million in 2001, according to VLSI Research. The decline in investment didn't lower costs for masks, because mask makers still must depreciate equipment purchases over five years, Hutcheson says.

ASICs under pressure

The problem of soaring mask costs is particularly acute for some suppliers of application-specific integrated circuits. Many ASICs are built into video games, digital cameras, mobile phones and other consumer products that sell millions of units. But others are custom-designed, low-volume chips for the military and health care devices such as CAT scanners. Makers of those ASICs are finding it increasingly hard to recover their up-front costs, which include photomasks. An ASIC run may total as few as 10,000 chips. So given 0.18-micron design rules and $260,000 for the mask set, the cost is $26 per chip.

"If they want only 50 or 100 working modules initially and the mask set costs $1 million, well, that's $10,000 per module," says Sematech's Kimmel. Hutcheson agrees. "At 130 nanometers, it balloons to $87 each, and that's for volumes of 10,000 units. The end market just won't sustain those prices."

By comparison, the memory chips and microprocessors in PCs are produced by the millions and their costs per mask set can be measured in pennies. Memory and microprocessor masks accounted for only about 10% and 5%, respectively, of mask volume in the year that ended in April 2002, according to Sematech's survey. ASICs and other logic devices accounted for a startling 70% of mask volume.

"If you squeeze some of the mask makers hard enough, they will admit that they actually charge more for memory masks and high-volume microprocessor masks, to essentially subsidize the lower prices on ASICs," says Kimmel.

The survey, which went largely unnoticed outside the mask industry, turned up some counterintuitive findings. About half the mask sets shipped were built to 0.50-micron or larger design rules. That node ramped 10 years ago. About 80% of masks shipped during the survey period were at 0.25-micron design rules or above. Costs for those mask sets are only about $25,000 and $85,000, respectively. That means that the vast majority of chips being sold are based on trailing-edge nodes, whose mask costs are relatively cheap compared to leading-edge designs.

Only a fraction of the mask output during the survey period was at 0.13-micron design rules. But reflecting the huge difference in costs between masks for trailing-edge technology and today's advanced masks, sets at the 0.13-micron node accounted for $700 million, or 28%, of the industry's $2.5 billion in revenue last year, according to VLSI Research. "This is why mask makers put such emphasis on leading-edge reticles," says Hutcheson. "They are the primary revenue-growth driver for the mask industry."

Rays of hope

The problem of expensive masks may have long-term implications for the chip industry. The high costs of photomasks are a factor in the decline in the number of new IC designs over the past five years. According to VLSI Research, there were 30,000 chip designs last year, down 23% from nearly 39,000 in 1998. The days when a handful of designers could set up workstations in a Silicon Valley garage and come up with an innovative chip design are virtually gone. They simply cannot afford to go into production.

"It's really stifling innovation," says Kimmel. "Typically, these new designs are going to demand the latest lithographic techniques and the most-costly masks."

To ameliorate costs, mask makers have responded with numerous products and services. Meanwhile, some vendors are offering targeted technologies that can help control costs between chip design and wafer tape-out. One of the more intriguing and speculative responses is what Sematech calls "maskless technology." It refers to various direct-write techniques that allow chip companies to bypass masks. The hope is that the companies can get at least enough wafers to test their devices before committing to volume runs and mask sets, Kimmel says. Last year, the International Technology Roadmap for Semiconductors (ITRS) put direct-write on the 65-nm semiconductor road map.

Deep-pocket concerns such as ASM Lithography, of Veldhoven, The Netherlands, and KLA-Tencor , San Jose, are backing some of this R&D. "These are savvy equipment companies. They don't just throw their money around," Kimmel says. Canon Inc. , Tokyo, and others are developing systems that expose millions of pixels at a time on a wafer. A programmable mask under development by Swedish firm Micronic Laser Systems AB uses an array of pixels that can be programmed instantaneously to reproduce a chip design. The problem with these systems, so far, and it's a big one, is throughput. They produce fewer than 5 wafers per hour, compared to 120 per hour for a state-of-the-art scanner.

In response to customer concerns about rising prices, DuPont Photomasks changed the way it describes itself from photomask maker to micro-imaging solutions provider, and it has enhanced its offerings. It started working more closely with designers at the front end of the process. DuPont also acquired BindKey Technologies Inc. , Sunnyvale, CA, which developed a software "cheat sheet" that shortens the time between design verification and tape-out. The program, which starts at $15,000, helps chip companies correct design violations and avoid new ones. That could cut back on the hours that highly paid designers typically spend in that intensive process. A beta version of a companion program would automatically fix design errors will be considerably more expensive. A one-year license to use it will cost $250,000, Blake said.

The delivery of 'pizza wafers'

Fabless Silicon Labs, which makes chips for communications products such as modems, set-top boxes and cellular handsets, takes a different route. It rides the Cybershuttle, Taiwan Semiconductor Manufacturing Company Ltd. 's response to mask-price inflation. The shuttle is a multiproject, or "pizza," wafer, ferrying designs at various design nodes from a variety of chip companies.

"We are sharing that multiproject wafer and the cost of that mask with other companies," says Daniel Artusi of Silicon Labs. "The Cybershuttle is like a train with fixed departure dates; you board when you have your design."

United Microelectronics Corp. , IBM and Chartered Semiconductor Manufacturing have versions of the multiproject wafer, says Kimmel. Although the programs give chip makers at least enough devices for design validation, he says, they are treading water until a better solution to escalating mask costs comes along. "The problem with Cybershuttle is that it doesn't represent a breakthrough. It's kind of a clever desperation move," Kimmel says.

Silicon Labs is happy to be on board, however. The company estimates that TSMC's Cybershuttle reduces its mask costs by at least 75%.

Artusi says TSMC's Cybershuttle allows Silicon Labs to "play with the big dogs in the semiconductor industry" by lowering its up-front costs. The company's largest customer is Seoul-based Samsung Electronics , which uses Silicon Labs' chips for its GSM cell phones. "The barriers to developing ICs using leading-edge technology are much lower," Artusi says. "In addition to the lower cost, we have shorter cycles through the fab, because several companies are sharing the same mask and wafer."

LSI Logic Corp. , Milpitas, CA, a leading producer of ASIC chips for the communications and storage markets, has watched its mask costs soar from $225,000 for 0.18-micron devices to $750,000 for 0.11-micron devices in the past five years. Ronnie Vasishta, vice president of ASIC technology marketing, expects mask prices to climb to $1.2 million for the 90-nm node.

In response to the climbing costs of both designs and masks, the company last year announced RapidChip, a platform product aimed at lowering the entry cost of custom-designed logic chips. It allows customers to add their own designs, or intellectual property, on top of a base platform of common components. That will help control mask costs, says Vasishta, and it means lower nonrecurring engineering costs to amortize on low-volume chips. The result is hybrid chips, rather than standard-cell ASICs.

"The only design-specific masks are a few metal masks," he says. "If the volume takes off, the RapidChip product can be migrated to an ASIC."

Dan Scovel, an industry analyst at Needham & Co., New York, NY, says LSI Logic and other ASIC makers continue to pass on the costs of photomasks to their customers. But the rising costs of design and mask-making mean that those companies are increasingly limited to high-volume chip applications. "There is a shrinking pool of volume customers," Scovel says.

Tom Blake, DuPont Photomasks' vice president of marketing, offers fabless chip makers a ray of hope of a different sort. He says the semiconductor industry has slowed its advance to next-generation ICs. If true, that will give fabless companies a respite from upgrading their chips every two years, which was the pattern of the 1990s.

Based on conversations with his customers and the failure of 0.13-micron devices to ramp last year as expected, Blake says the industry is returning to its historical pattern of ramping next-generation devices every three years.

"People will still claim that they are maybe closer to the two-year cycle and that they're pushing the envelope of 65nm now," Blake says. "But it's an admission, finally, by the industry that we're going to have to go back to three-year cycles."

That's not entirely true, counters Gartner Dataquest's Smith. Although many fabless companies that rely on foundries for both mask making and wafer production may be slowing to three-year cycles, the major integrated device manufacturers (IDMs), such as Intel and IBM, are maintaining their breakneck pace toward the next-generation nodes.

"What we have seen is that the super IDMs have been able to maintain the two-year road map," Smith says. Partly because of that, high-end fabless vendors such as San Jose-based Xilinx Inc. and Nvidia Corp. , Santa Clara, CA, among others, have taken their foundry business to IBM. Those foundry contracts are one reason Gartner Dataquest believes that IBM has overtaken Singapore-based Chartered as No. 3 in global foundry revenue.

Like Smith, IBM's Reeves believes that the industry may be making too much of the rise in mask costs. Reeves says prices are starting to come down as mask makers are finding ways to produce some reticles with less-costly processes but with newer tools.

"Although there was great press coverage that 90-nanometer mask sets in 2002 were $1.3 million per set," Reeves notes, "the price has already dropped in 2003 to $800,000 per set."

How will expensive photomasks affect the way you do business? Send your insights to feedback@eb.reedbusiness.com .

Jerry Mahoney is a freelance writer in Austin who has covered the tech industry for the past 12 years. E-mail him at jerrymahoney@irland.com