SUNNYVALE, Calif.--(BUSINESS WIRE)--March 25, 1996--Orbit Semiconductor Inc. (NASDAQ:ORRA) today announced that it is expanding its ENCORE! FPGA-to-gate-array conversion program to include application specific integrated circuit (ASIC) designs, which have never been simulated, and therefore have no test vectors for design-conversion verification.

Now, through the use of standard automatic test pattern generation (ATPG) tools integrated with Orbit's proprietary software, Orbit is able to offer its ENCORE! conversion service to customers with unsimulated programmable logic devices.

In the first phase of its "no-vectors" program, Orbit is making available ENCORE! conversions for Xilinx 3000 and 4000 series FPGAs (field programmable gate arrays) and Advanced Micro Devices (AMD) Mach and PAL-series chips. Other manufacturers' FPGAs will be addressed by Orbit's "no-vectors" program later in the year.

"Our customers with unsimulated programmable devices have frequently expressed interest in Orbit's ENCORE! program," said Stephen Gold, vice president of marketing, Reptron Electronics Inc.

"Now with ENCORE! expanded to include unsimulated Xilinx and AMD Mach chips, we will be able to offer many of them the benefits of lower cost, enhanced performance and/or accelerated delivery associated with Orbit's gate array conversions."

"With more than 750 ENCORE! designs completed to date, our FPGA-to-gate array conversion service is a proven, low-risk program," said Gary Kennedy, Orbit president and chief executive officer.

"For no-vectors conversions, we have developed a profile for `standard' designs. Unsimulated FPGAs which meet our standard criteria should flow through the conversion process in approximately six weeks. The process is also suitable for increasing fault coverage for designs that have inadequate test vectors."

ENCORE! is a netlist conversion service featuring a direct replacement of FPGAs or programmable devices by Orbit's gate array technology. ENCORE! provides customers the benefits of low-cost, high-performance gate arrays as well as quick-turn service, packaging flexibility and low minimum-volume requirements.

The program is centered on design methodologies that support system designers with many engineering flexibilities such as programmable power supplies, packaging options and the ability to merge multiple designs into a single gate array.