Amulet Technologies LLC in Santa Clara had a problem. The fabless chip company had designed a graphics engine for an embedded system. It wasn't a high-volume application, but the company still expected to ship as many as 100,000 of the chips. Amulet had designed the original prototype as an FPGA, but as the chip entered production, Amulet wanted to slash the costs with a more efficient ASIC design. A few years ago, an ASIC would have been the natural choice. But not anymore.

The cost of making masks for ASICs has soared from $100,000 in 0.5-micron fabs five years ago to as much as $1 million today in 0.13-micron fabs, according to Jordan Selburn, an analyst at iSuppli Corp., a market research firm in El Segundo, CA. With the coming of 90nm production during the next year, mask costs could rise to $2 million, says Selburn. And as complexity grows, so does the risk that design and verification time will take too long. That means that as the costs of doing an ASIC rise, so does the breakeven point on the number of chips that must be sold to justify the upfront costs.

"We're talking 10,000 to 100,000 units selling for $10 to $20, so we wouldn't have been able to bear the engineering costs of an ASIC," says Ken Klask, president of Amulet. "And the ASIC would have taken us twice as long to design."

So Amulet turned to a hybrid of an ASIC and an FPGA. Chip Express Corp. , Santa Clara, CA, had tools and blocks of pre-designed chip components that enabled Amulet to snap together a "modular array" in a matter of weeks. The array combined Amulet's own custom-designed microprocessor core with generic features, like memory components, from Chip Express. Chip Express then took the design into a third-party foundry, which already had half-finished gate array chips in the works. Chip Express customized the gate arrays by adding the final layers of metal to the chips.

Welcome to the middle

The soaring cost of ASICs means more and more OEMs find themselves in a predicament like Amulet's. And increasingly, more chip makers are recognizing that there may be a market opportunity in filling the growing gap between FPGAs and ASICs.

"The number of ASIC designs is going down and they're becoming more complex," says Rick Marz, executive vice president for communications at LSI Logic Corp. , Milpitas, CA. "We looked at this and saw something had to happen to change the return on investment model for our customers."

Indeed, the drop in the number of ASIC designs in recent years is significant. Only 4,300 ASIC designs were started in 2002, down from about 10,000 five years ago, according to Gartner Dataquest. Designs were off 36% in 2001 and will be off 12% in 2002. Selburn at iSuppli believes that ASIC design numbers were even less than Gartner Dataquest's numbers—around 2,100 design starts in 2001—and he believes the number will fall 17% from 2001 to 2006 and that ASIC revenues will fall 22% from $16.2 billion in 2000 to $12.6 billion in 2006. (See chart, page 49.)

Chip companies are trying to fill the gap in several ways. Some, like Chip Express, are providing hybrid devices that combine features of FPGAs and ASICs. Others are trying to be more efficient with design. And fabless ASIC companies, allied with contract manufacturers and third-party tool makers, are aiming to be more efficient than the big ASIC vendors.

FPGAs have been putting pressure on ASICs because of Moore's Law. As chip density improves, the cost penalty for the less efficient FPGA architecture is falling relative to ASICs. Xilinx Inc. expects to deliver a 1-million-gate FPGA this spring for $25, compared to $3,000 for a 1-million-gate FPGA a few years ago, says Sandeep Vij, vice president of marketing at Xilinx, an FPGA vendor in San Jose, CA.

"Moore's Law is helping us close the gap, and so we're skiing downhill," Vij says. "ASICs are trying to ski up the mountain as their design and prototyping costs go up."

In fact, programmable logic (which includes FPGAs) will grow 16% from 2001 to 2006, according to Bryan Lewis, chief semiconductor analyst at Gartner Dataquest.

Best of both worlds?

Several companies are marketing chips that represent a hybrid approach. In addition to Chip Express, AMI Semiconductor Inc. , Pocatello, ID, offers a hybrid device that is customizable, low cost and quick to market, says Vince Hopkin, vice president of digital ASICs at AMI. The company launched its XPress Array products in January 2002 in partnership with foundry Taiwan Semiconductor Manufacturing Co. , Hsinchu Park, Taiwan. AMI is marketing the service as "FPGA conversion" and has been focusing on devices that use trailing-edge manufacturing technology.

Lightspeed Semiconductor , Santa Clara, CA, is another fabless modular array company in the hybrid device market. The company is trying to distinguish itself from others by going to smaller manufacturing geometries quickly, allowing it to build parts that run at speeds up to 700 MHz.

"We think we'll be in the sweet spot for a lot of designs," says Michael Sydow, vice president of marketing at Lightspeed.

Critics dismiss such solutions as neither fish nor fowl, and add that they are not particularly new. Such chips arbitrarily limit the functionality of the design, and are just a repeat of the tired and inefficient strategy of customizing the final layers of a gate array, they say.

"I'm not sure there is a middle ground," says Barry Marsh, vice president of product marketing at Actel Corp. , a maker of FPGAs in Sunnyvale, CA. "The idea of a reprogrammable ASIC has been the Holy Grail forever. The guys trying to do this are kidding themselves." Marsh maintains that FPGAs are good enough in performance and cost for an increasingly large piece of the overall semi-custom chip market, and offers as proof the fact that ASICs continue to lose ground to FPGAs.

But big ASIC companies like LSI Logic and Japan's NEC Corp. , Tokyo, are endorsing hybrid devices that are both semi-customizable and have a faster time to market than standard cell ASICs, which are now more common than gate arrays.

LSI launched the first of its RapidChip modular arrays in January 2003. The product resembles the early gate arrays, which consisted of a sea of uniform gates connected by a few layers of metal. These early gate arrays didn't allow much flexibility in design, resulting in poor performance, and they became costlier to make with multiple metal layers.

With RapidChip, however, LSI will prefabricate a base platform wafer except for the last few layers of metal. The base platform will include functional building blocks such as common input-output components or microprocessor cores. Using such components cuts down on the number of wasted gates and delivers a product that makes more optimal use of the silicon than the older gate arrays. Then the customer can take the base platform and add its own intellectual property, specifying the design of the final layers of metal. The design differs from the old gate arrays because of the larger numbers of layers of metal, an advanced manufacturing process, more functionality built into the base layer, and the ease of adding new functions through LSI's library of component designs.

"We want to define a product that delivers most of what the customer wants for a cell-based ASIC, with less than half the time for design, yet 20 times the performance of an FPGA and a tenth of the cost," says LSI's Marz.

LSI can produce a RapidChip prototype with 80% of the performance of an equivalent ASIC and bring it to volume production in six months, much shorter than the 12 months to 18 months for an ASIC, claims Marz. Target customers include makers of DVD players, who may be able to come up with several different models using the same base RapidChip device.

Some critics cover their bets

Rivals say it can't be done. Tom Reeves, vice president of ASICs at IBM, says that approaches like RapidChip often result in base platforms that "don't have enough commonality to be useful." That is, Reeves believes that even similar chips like those that will fit inside a DVD player or a set-top box must be designed independently in order to maximize performance and efficiency. Very little is gained by having a common design for all but minimally different functions of the chips, he says.

Rather than turning to hybrids, the solution is to cut the time it takes to design an ASIC and make sure it works the first time, say critics. IBM can now finish a system-on-chip (SoC) design in just four months, compared to 18 months or more in 1998, and more than half of all initial prototypes work the first time, claims Reeves. Such results came from a shift to platform-based design, where customers plug in modules from component libraries. That has helped IBM hang on to the No. 1 position in ASICs for three years, says iSuppli's Selburn.

Despite its protests, IBM is trying out some hybrid devices of its own, largely as a contingency plan in case high-end customers want the choice of functions and performance, says Reeves. IBM and Xilinx have created an alliance to marry ASICs with FPGAs. Starting next year with its 90nm process, which will allow a dramatic increase in transistors per chip, IBM plans to allow customers to embed a Xilinx FPGA core in an ASIC. That kind of approach may work on the high end, but it remains to be seen if it will be cost effective in the mainstream, says Lewis at Gartner Dataquest. Tensilica Inc. , Santa Clara, CA, also contends that embedding its customizable microprocessor cores in ASICs is another way to marry the benefits of flexibility and high performance.

Design tool makers like Monterey Design Systems , Sunnyvale, CA, and ReShape Inc. , Mountain View, CA, also are creating tools that shorten the time it takes to design or layout chips. ReShape will sell its tools to ASIC designers but also offers a service to do the physical layout of the chip itself, helping to shave time off the schedule.

ESilicon Corp. , Sunnyvale, CA, has created tools to try to reduce the time it takes to physically lay out the logic design, shaving weeks off a process that once took months. Using tools that operate on a higher level of abstraction than traditional tools, they take a completed design and convert it so it can be made in a particular fab. But eSilicon goes beyond ReShape by using TSMC's fabs to make chips for its customers. That allows eSilicon to sell the chips for a lower price because it doesn't have to amortize a factory, says Jack Harding, CEO of eSilicon.

"Larger customers and foundries like us because we give them a single point of contact," Harding says. "We manage the supply chain in getting a chip done, and we get a volume discount from the foundry because we're ordering millions of chips for dozens of our customers. Think of us as the Price Club for chips."

There seems to be plenty of evidence that ASICs are becoming too costly and complex for some OEM customers. But the open question is whether any of these new approaches will get much traction during the recession.

"It will take a while for things to take off in any direction," says Gartner Dataquest's Lewis, "since nobody is buying anything now."

Dean Takahashi is a staff writer at the San Jose Mercury News. E-mail him at dtakahashi@sjmercury.com .