Circuit-board design for 10-Gbit XFP optical modules

The XFP MSA (10-Gbit small-form-factor-pluggable multisource-agreement) group, which defined a 10-Gbps serial transceiver for datacom and telecom applications, comprises leading networking, system, optical-module, semiconductor, and connector companies from both the datacom and the telecom industries

(Reference 1 ). Founding member companies, which launched the group in 2001, include Broadcom Corp, Brocade, Emulex Corp, Finisar, JDS Uniphase, Maxim Integrated Products, ONI Systems, ICS (a Sumitomo Electric company), Tyco Electronics, and Velio. Currently, more than 60 companies specializing in optics, ICs, and system implementation have joined the XFP MSA as contributors and adopters.

An XFP module is a hot-pluggable, small-footprint, serial-to-serial optical transceiver that supports SONET OC-192, 10-Gbps Ethernet, 10-Gbps Fibre Channel, and G.709 links. A typical XFP-module application includes the module, the host board, a cage assembly, and a heat sink (Figure 1 ). The module measures 78×18.4×8.5 mm.

XFP devices are small because most of their electronic signal processing resides on the host board rather than within the module itself. Older form factors, such as Xenpak and the telecom industry's 300-pin XBI modules, require XAUI (10-Gbit-attachment-unit-interface) transceivers and multiplexer/demultiplexer devices, respectively, increasing size, complexity, and power requirements. The new XFP form factor features XFI—a 10-Gbps serial electrical interface that places most of the electronic-signal-processing functions within the transceiver ASIC on the system pc board rather than within the optical-transceiver module.

Placing the transceiver ASIC on the system pc board, however, requires system designers to implement 10-Gbps serial interfaces on traditional FR4 pc boards. Engineers must take special care to ensure that the interface provides sufficient signal amplitude and fidelity after traversing 8 to 12 in. of pc-board interconnect. The interconnect may include microstrip traces, stripline traces, or both; layer-to-layer via structures; a 30-pin connector; and a BGA ASIC package. This article provides design guidelines for the high-speed electrical interfaces in XFP applications. Design examples demonstrate that application of simulation software can accelerate successful pc-board design for XFP adopters.

System overview

XFI is a differentially signaled, serial interconnect with a nominal baud rate of 9.95 to 10.75 Gbps. Transmitting and receiving signals are ac-coupled, 100Ω differential pairs.

A typical end-to-end electrical channel for XFP applications includes a transceiver board that exists within the XFP module; a 30-pin, hot-swappable connector; a host board; and a BGA package (Figure 2 ). Although few host-board designers have direct control over the transceiver ASIC BGA package, it is nevertheless important to mention that you can simulate, design, and include the package in channel simulations at 10 Gbps.

Simulations and measurements of this electrical channel provide guidelines for XFI design. In the stackup for the evaluation board, total board thickness is 36 mils, and the board material is standard FR4 with εr =4 and a loss tangent of 0.016. All traces are 1/2-oz. copper (Figure 3 ).

The most prominent feature of the XFI is the attenuation of the transmitted signal across the pc board. Designers of pc boards with FR4 dielectric substrates never intended them to support signals at 10 Gbps; the dielectric loss at high frequencies provides the dominant impairment. Typical microstrip differential transmission lines on FR4 exhibit insertion loss of roughly 0.5 dB/in. at 5 GHz and 0.9 dB/in. at 10 GHz. This loss effectively performs a lowpass filtering of the transmitted digital signals. Therefore, it severely limits the distance that uncompensated 10-Gbps digital signals can propagate on pc-board transmission lines. Fortunately, modern signal-conditioning circuits in the transceiver ASICs and within the XFP modules can compensate for this filtering and enable transmission distances to 12 in. The challenge for the host-board designer is to provide transmission lines with the proper characteristic impedance and routing and via designs that have sufficiently low return loss.

Vias

Via structures allow pc-board designers to route circuit traces between layers of a multilayer board. Vias may be particularly useful to make the transition from the pins of a BGA or connector down to stripline traces within a host or transceiver board. The most common and inexpensive via structure is the so-called through-hole via. You create a through-hole via by drilling all the way through a pc board followed by a plating process. The plating process provides electrical continuity to top and buried traces by virtue of signal pads on the desired layers. Alternatives to through-hole vias are blind vias and back-drilled vias. Although these alternatives may provide higher performance, industry experts generally believe that most XFP adopters will use the lower cost through-hole via for volume manufacturing.

A single-ended through-hole via provides a transition from the top layer to the next adjacent layer in a 16-layer pc board (Figure 4 ). Only the portion of the via between the adjacent layers provides an electrical path. The remaining portion provides an electrically short, open-circuited transmission-line stub. The resulting additional reactance lowers the characteristic impedance, thereby causing reflections. A better approach is to route traces (Figure 5 ). Moving from the top layer to a layer on or near the opposite side of the board minimizes the size of the open-circuited stub, thus minimizing electrical reflections.

The Ansoft HFSS (high-frequency structure simulator) performs full-wave, 3-D electromagnetic simulations, and you can use it to evaluate the relative performance of via structures with and without open-circuited stubs. Figure 6 plots the extracted S-parameters for transitions from the top layer to various layers of a 16-layer pc board. The red curve is for trace routing from the top to the bottom layer and yields the best performance, or lowest reflections. Moving from the top layer to a layer near or on the opposite side of the board minimizes the size of the open-circuited stub and, hence, electrical reflections.

Because the XFI is differentially signaled, vias occur in pairs. These differential vias route signals from top-layer microstrip traces down to buried stripline traces. A differential-via geometry has a pair of via structures traversing several power and ground planes on a 100-mil-thick, multilayer pc board (Figure 7). Critical dimensions are via diameter (drill size), pad diameter, gap between the pad and the ground/power-plane cutout, and via pitch. Full-wave, 3-D electromagnetic simulations identify dimensions that would minimize reflections and provide the best signal fidelity. Tunable parameters are via pitch and gap.

A parametric sweep of via pitch and gap reveal that you can achieve the best performance for 100- and 62-mil-thick boards using the dimensions that Table 1 outlines (Figure 8 ). Interestingly, the dimensions for both board depths are identical. Considering the via structure as a transmission line with propagation along the dimension perpendicular to the pc-board plane, it is intuitive that this transmission line should have a uniform cross section that is independent of the length of the line (board thickness).

You can improve the traditional differential via using a GSSG (ground-signal-signal-ground) geometry. The GSSG differential via comprises four single-ended vias (Figure 9 ). The two inner vias are the differential signal lines, and the two outer vias are ground-return lines. Although differential signaling generally provides for all return-path currents, the GSSG geometry can support common-mode signals with a well-controlled return-current path. Any coupled or generated common-mode signals propagate through the via (rather than being scattered) and along the transmission line to the receiver where it terminates.

Critical dimensions for the GSSG geometry are via diameter (drill size), pad diameter, gap between pad and ground/power-plane cutout, via pitch, and via-to-ground-via gap. The additional conductors of the GSSG structure provide more tunable parameters that can in turn provide optimal performance. Table 2 presents four alternative GSSG via-dimension combinations that offer acceptable performance. Figure 10 shows plots of the extracted S-parameters for those four alternative geometries.

End-to-end channel simulation

This analysis extracts S-parameter models using circuit simulation, electromagnetic simulation, and a combination of both. It is desirable to combine these results in a single simulation to examine the end-to-end performance of an XFP implementation. A convenient method of combining these results is to use a high-frequency system simulator, such as the one in Ansoft Designer. The system simulator can provide not only the frequency-domain results for the system, but also the transient results and system-level metrics, such as eye diagrams and bit-error-rate plots.

The system simulator model for the XFP channel of Figure 2 includes the transceiver-board traces, the Tyco connector, and the host-board traces. Cascaded S-parameter models that you compute from the circuit and electromagnetic simulations allow you to evaluate end-to-end system performance (Figure 11). Figure 12 compares the simulated and the measured differential S-parameters for SDD11 and SDD21 , respectively. Although differences exist between the simulated and the measured results (especially for SDD11 ), the simulations clearly and accurately depict the overall system-response trends. Figure 13 shows the measured and simulated eye diagrams for the XFP channel of Figure 2 .

	Gap (mm)	Via pitch (mm)	Drill size (mm)	Pad diameter (mm)
100-mil board	0.52	0.8	0.30 (12 mil)	0.56 (22 mil)
62-mil board	0.52	0.8	0.30 (12 mil)	0.56 (22 mil)

Gap (mm)	Via pitch (mm)	Via-to-ground (mm)	Drill size (mm)	Pad diameter (mm)
0.32	1	0.7	0.30 (12 mil)	0.56 (22 mil)
0.32	1	1	0.30 (12 mil)	0.56 (22 mil)
0.52	0.8	0.7	0.30 (12 mil)	0.56 (22 mil)
0.52	0.8	1	0.30 (12 mil)	0.56 (22 mil)

Lawrence Williams, PhD, is director of business development at Ansoft Corp, where he is responsible for building strategic relationships with Ansoft customers and business partners. He was responsible for the strategic and technical direction of Ansoft HFSS, has more than 16 years of experience in electromagnetics and communications engineering, and has published numerous technical papers. Williams held various senior-engineering positions in the Engineering Division of Hughes Aircraft Co, Radar Systems Group. He received his master's, engineering, and PhD degrees from the University of California—Los Angeles.

Steve Rousselle joined Ansoft Corp in 1999. He serves as an application-engineering manager. He created the High-Speed Signal Integrity Design course for Ansoft HFSS, has published several articles on electromagnetic simulation, and has presented numerous courses and seminars on signal integrity and electromagnetic simulations with Ansoft products. Before Ansoft, he worked at TRW and Delphi Automotive as an antenna-system design engineer. He holds BSEE and MSEE degrees from Michigan Technological University (Houghton).

Bryan Boots joined Ansoft Corp in 2000 as an application engineer for high-frequency products. He holds BSEE and MSEE degrees from the University of Colorado—Boulder, where his studies included an emphasis on computational electromagnetics

Reference

1. XFP MSA, www.xfpmsa.org .

Acknowledgments

Thanks to Ali Ghiasi of Broadcom Corp for providing the transceiver and host-board geometries and measurements, Michael Fogg of Tyco Electronics, Daniel Wu of Ansoft Corp for the via simulations and optimizations; and Eldon Staggs of Ansoft Corp for the end-to-end system simulation.